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主芯片和MCU

MCU單片機(jī)/STM32F407VGT6

STM32F407VGT6

High-performance foundation line, Arm Cortex-M4 core with DSP and FPU, 1 Mbyte of Flash memory, 168 MHz CPU, ART Accelerator, Ethernet, FSMC

產(chǎn)品特性

The STM32F405xx and STM32F407xx family is based on the high-performance Arm? Cortex?-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces.


  • 4.3 μA Stop 3 mode with full SRAM
  • 4.0 μA Stop 2 mode with 16-Kbyte SRAM
  • 8.95 μA Stop 2 mode with full SRAM
  • 19.5 μA/MHz Run mode @ 3.3 V
  • Core
    • Arm? 32-bit Cortex?-M33 CPU with TrustZone?, MPU, DSP, and FPU
  • ART Accelerator
    • 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and external memories: up to 160 MHz, 240 DMIPS
    • 4-Kbyte data cache for external memories
  • Power management
    • Embedded regulator (LDO) and SMPSstep-down converter supporting switchon-the-fly and voltage scaling
  • Benchmarks
    • 1.5 DMIPS/MHz (Drystone 2.1)
    • 651 CoreMark? (4.07 CoreMark?/MHz)
    • 535 ULPMark?-CP
    • 149 ULPMark?-PP
    • 58.2 ULPMark?-CM
    • 133000 SecureMark?-TLS
  • Memories
    • 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles
    • 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON
    • External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories
    • 2 Octo-SPI memory interfaces
  • Security and cryptography
    • PSA level 3 and SESIP level 3 certified
    • Arm? TrustZone? and securable I/Os, memories and peripherals
    • Flexible life cycle scheme with RDP and password protected debug
    • Root of trust thanks to unique boot entry and secure hide protection area (HDP)
    • Secure firmware installation (SFI) thanks to embedded root secure services (RSS)
    • Secure data storage with hardware unique key (HUK)
    • Secure firmware upgrade support with TF-M
    • 2 AES coprocessors including one withDPA resistance
    • Public key accelerator, DPA resistant
    • On-the-fly decryption of Octo-SPI external memories
    • HASH hardware accelerator
    • True random number generator, NIST SP800-90B compliant
    • 96-bit unique ID
    • 512-byte OTP (one-time programmable)
    • Active tampers
  • Clock management
    • 4 to 50 MHz crystal oscillator
    • 32 kHz crystal oscillator for RTC (LSE)
    • Internal 16 MHz factory-trimmed RC (±1%)
    • Internal low-power 32 kHz RC (±5%)
    • 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by LSE (better than ±0.25% accuracy)
    • Internal 48 MHz with clock recovery
    • 3 PLLs for system clock, USB, audio, ADC
  • General-purpose input/outputs
    • Up to 136 fast I/Os with interrupt capability most 5V-tolerant and up to 14 I/Os with independent supply down to 1.08 V
  • Up to 17 timers and 2 watchdogs
    • 2 16-bit advanced motor-control, 4 32-bit, 5 16-bit, 4 low-power 16-bit (available in Stop mode), 2 SysTick timers and 2 watchdogs
    • RTC with hardware calendar and calibration
  • Up to 22 communication peripherals
    • 1 USB Type-C?/USB power delivery controller
    • 1 USB OTG 2.0 full-speed controller
    • 2 SAIs (serial-audio interface)
    • 4 I2C FM+(1 Mbit/s), SMBus/PMBus?
    • 6 USARTs (ISO 7816, LIN, IrDA, modem)
    • 3 SPIs (5x SPIs with the dual OCTOSPI)
    • 1 CAN FD controller
    • 2 SDMMC interfaces
    • 1 multi-function digital filter (6 filters)+ 1 audio digital filter with sound-activity detection
    • Parallel synchronous slave interface
  • 16- and 4-channel DMA controllers, functional in Stop mode
  • Graphic features
    • Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
    • 1 digital camera interface
  • Mathematical co-processor
    • CORDIC for trigonometric functions acceleration
    • Filter mathematical accelerator (FMAC)
  • Up to 22 capacitive sensing channels
    • Support touch key, linear and rotary touch sensors
  • Rich analog peripherals (independent supply)
    • 14-bit ADC 2.5-Msps with hardware oversampling
    • 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
    • 2 12-bit DAC, low-power sample and hold
    • 2 operational amplifiers with built-in PGA
    • 2 ultra-low-power comparators
    • Development support: serial-wire debug (SWD), JTAG, Embedded Trace Macrocell? (ETM)
  • ECOPACK2 compliant package
產(chǎn)品應(yīng)用

INDUSTRIAL

規(guī)格
型號(hào)DataSheetDimension (mm)Description